This work reports GaN power high-electron-mobility transistors (HEMTs) that achieve a breakdown voltage (BV) exceeding 2400 V (defined IDSS <1 μA mm-¹)) through the implementation of a single gate field plate (FP). This design establishes a simplified yet optimized electric field profile, which is key to achieving a high BV while maintaining favorable dynamic performance. The dynamic ON-resistance (Ron) remains as low as 106% after OFF-state VDS stress at 600 V. The combination of high BV and robust dynamic characteristics demonstrates that the single gate FP technique is a promising approach for the mass production of high-performance GaN power HEMTs, offering the potential for reduced process complexity and cost without compromising device performance. © 2026 The Author(s). Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd

Fig. 1. (a) Schematic of the cross-section of a GaN HEMT with a single field plate (b) microscopic image of the 2 inch wafer post-process completion (c) microscopic image of the fabricated GaN HEMT with a single field plate (d) focused ion beam (FIB) image of the fabricated GaN HEMT with a single field plate.

Fig. 2. Key process nodes of the GaN HEMT with a single field plate.

Fig. 3. SEM image of the GaN HEMT passivated with (a) ICPCVD (wafer A) and (b) PECVD.

Fig. 4. Output characteristics of the GaN HEMT.

3.1. Static breakdown characteristics and mechanisms via electric field simulation

Figure 5 depicts the OFF-state breakdown characteristics of the fabricated GaN HEMTs. A bias voltage of −15 V was applied to the gate, 0 V to the source, and the substrate was left floating. Wafer A, featuring ICPCVD SiN passivation, exhibits a BV higher than 2000 V for 44% of its devices. In contrast, wafer B with PECVD SiN passivation shows that nearly 70% of its devices have a BV exceeding 2400 V. The OFF-state leakage current IDSS is approximately 20 μA for wafer A and 1 μA for wafer B at a drain-source voltage VDS of 2000 V, as illustrated in Figs. 5(c) and 5(e), respectively. The marked reduction in IDSS leakage for wafer B compared to wafer A is attributed to superior passivation of surface defects under the higher deposition temperature of PECVD (350 °C), as suggested by the SEM images in Fig. 3. The substantial improvement in BV uniformity and IDSS leakage for wafer B (PECVD at 350 °C) over wafer A (ICPCVD at 250 °C) underscores the critical role of deposition tempera-ture. Higher temperature promotes better interface repair, film stoichiometry, and hydrogen redistribution, all of which enhance dielectric robustness and interface quality. For both wafers, IDSS increases rapidly after a high voltage beyond 2000 or 2400 V, indicating that the breakdown is caused by a vertical failure mode which occurs beyond the lateral failure mode that happens between the gate and drain electrodes.25) The single-FP applied in our work extends the lateral failure mode and postpones the vertical failure mode compared to multiple-FP, and thus can increase BV, as indicated by the comparison between our work and reference,19) which has the same buffer structure. Table I summarizes the blocking capabilities of various 1200 V rated GaN power HEMTs. Benchmarking against state-of-the-art multiple-FP designs in Table I reveals that our single-FP device achieves a superior BV while maintaining exceptionally low IDSS leakage. This demonstrates that careful single-FP optimization can match the static performance of more complex architectures. The physics is further explained with the Silvaco simulation results in Fig. 6(b). From Fig. 6(a), the IDSS leakage is reduced at the same VDS bias as the gate FP dielectric thickness increases from 150 nm to 300 nm. This is accom-panied by the reduction in the electric field peak at the gate FP edge, as shown in Fig. 6(b). Once the electric field peak at the drain edge exceeds the breakdown strength of the GaN material, the IDSS leakage is no longer reduced. The relatively low IDSS leakage in our work as compared to the reference works is attributed to the simplified electric field peak condition indicated from the Silvaco simulation, as fewer weak points would be present when the number of electric field peaks is reduced.26) In the GaN-on-Si epitaxial structure of this work, the highly resistive carbon-doped buffer layer and the conductive silicon substrate jointly govern the vertical breakdown path. At extremely high drain bias (>2000 V), the vertical electric field promotes electron injection from the substrate into the buffer. These electrons are captured by deep-level traps, forming space charge that distorts the field distribution and leads to localized Joule heating, eventually triggering thermal runaway and the transition to the vertical failure mode. The achievement of >2400 V BV on a conductive Si substrate demonstrates the effectiveness of the single-FP design in managing the lateral field and postponing vertical breakdown. This potential highlights its suitability for more demanding applications, such as 1200 V and higher-voltage power markets where insulating substrates are typically employed.11,17)

3.2. Thermal dissipation analysis

At high switching frequencies (e.g. >100 kHz), reduced cooling time between cycles will lead to an elevated average channel temperature. This may affect dynamic Ron through two primary physical pathways: (i) increased emission rates from existing traps, which could partially recover collapse; and (ii) possible activation of deeper traps or enhanced interface state generation under cyclic thermo-mechanical stress, which may ultimately degrade high-frequency perfor-mance. Despite the complexity of real operating conditions, our single-FP design offers inherent thermal advantages: our device exhibits uniform interfaces between semiconductor and passivation/dielectric layers (Fig. 1) and excellent planarity (Fig. 3), both of which are crucial for efficient vertical heat conduction from the channel toward the substrate. In contrast, multiple-layer, non-planar structures with multiple-FP can introduce thermal bottlenecks at a) BV is normalized by LGD.

topographic steps. Therefore, our simplified single-FP archi-tecture is favorable for/offers inherent advantages for thermal management.

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