Abstract
Since the junction temperature is a critical factor determining the lifetime and reliability of LEDs, effective thermal management is essential to prevent premature failure. This study uses COMSOL Multiphysics® to simulate a 10 W multi-chip COB LED package, focusing on the role of thermally conductive adhesive films. Results show that junction temperature is more sensitive to film thickness than to thermal conductivity. Reducing thickness from 0.6 mm to 0.1 mm gradually improves cooling, with diminishing returns below 0.1 mm. Similarly, thermal conductivity above 5 W/m·K offers limited improvement. Dense chip layouts intensify the film’s influence. Optimizing these parameters effectively reduces local overheating and enhances dissipation. This study provides practical guidelines for enhancing the long-term reliability of high-density LED packaging by strategically optimizing adhesive film parameters to mitigate thermal-induced degradation.
Keywords: multi-chip COB LED; thermal management; finite element simulation; adhesive film
1. Introduction
The Chip-on-Board (COB) packaging method is a mature and mainstream technology for LED light sources, offering high integration, high luminous efficacy, excellent color rendering, uniform illumination, and healthy lighting performance. Additionally, it features low cost, efficient heat dissipation, and extended service life. However, as chip packaging density and high-power devices advance, high junction temperatures in LEDs significantly impair their electrical characteristics, optical performance, and reliability [1-4]. With lamp and luminaire design optimization nearing saturation [5], enhancing the performance of COB carrier boards has become a crucial issue.
Bang [6] improved the package structure of LEDs by adding a ceramic segmentation layer to optimize the package structure of the LEDs and reduced the junction temperature of the LEDs from 114℃ to 109℃. Xia [7] employed finite element simulations to analyze the thermal distribution of deep ultraviolet LEDs with varying packaging densities on three commonly used COB substrates. Wang et al. [8] investigated the effects of different soldering temperatures on the performance of COB light sources during vacuum reflow soldering. Experiments were conducted at soldering temperatures of 250℃, 260 °C, 270 °C, 280 °C, and 290 °C, examining the influence on void ratio, steady-state voltage, luminous flux, luminous efficacy, and junction temperature. The results demonstrated that soldering at 270 °C yielded the best overall performance and the highest reliability, which was further validated through practical application and aging tests. Yu [9] implemented microlens arrays on a flat encapsulation layer to improve the light efficiency of COB-LED light sources, and the microlens arrays with optimal geometries improved the light efficiency of blue and white light sources by 50.9% and 9.31%, respectively, compared to the conventional flat encapsulation layer. Lee [10] et al. investigated the thermal behaviors of high-power LED packages to improve the thermal performance of low-temperature co-fired on-board ceramic chip (LTCC-COB) packages. Thermal analysis shows that the improved LTCC-COB package design is comparable to metal lead frame packages with low thermal resistance. Kim et al. [11] found that the use of a silicon substrate as the chip substrate reduces the junction temperature and packaging cost of the chip.
Jiang et al. [12] developed a hybrid thermal interface material (TIM) with high thermal conductivity by integrating two-dimensional boron nitride nanosheets (BNNS) and liquid metal (LM) nanoparticles as thermal conductive fillers into a photopolymerizable polydimethylsiloxane (PDMS) matrix. This composite maintains excellent electrical insulation and mechanical stability under repeated deformation, ensuring long-term reliability. Significant improvements in heat dissipation and device performance were observed in LEDs, batteries, and flexible thermoelectric devices. Kim [13] et al. demonstrated mechanically robust, bidirectionally thermally conductive materials by micro-molding boron nitride (BN) micro-scale flakes (µ-flakes) dispersed within a polymer matrix. The resulting TIM is applicable to high-power, high-temperature, and mechanically deformed environments in 3D integrated electronics. Chen et al. [14] modified diamond powder using sodium silicate as an inorganic matrix to create a thermal conductive filler. Optimal bonding and thermal conductivity were achieved at diamond mass fractions between 50% and 60%, establishing this as a promising new thermal material capable of replacing organic thermal pastes. Wang et al. [15] enhanced the thermal conductivity of epoxy resin by incorporating a three-dimensional boron nitride thermal network. This approach provides a new direction for developing high-thermal-conductivity insulating materials for power semiconductor packaging.
Controlling the junction temperature delays the thermal failure process, thereby enhancing the device’s reliability and lifetime. This study focuses on the thermally conductive adhesive film, a critical layer in the substrate responsible for electrical insulation and heat conduction, to investigate how its thickness and thermal conductivity influence the optothermal performance of COB light sources. A three-dimensional numerical model was developed and validated experimentally for reliability.
While thermal analysis and thermal resistance modeling for COB packages have been extensively reported and the concept of extended thermal resistance is well established, existing studies predominantly focus on the overall package structure or heat sink optimization. The present work is centered on thermally conductive adhesive film—a key interface material—and systematically quantifies the coupled effects of its thermal conductivity and thickness on the junction temperature of high-density multi-chip COB devices. Moreover, through thermal resistance network analysis, this study reveals the physical mechanism of dynamic thermal bottleneck shift during the optimization of adhesive film parameters. This mechanism provides a new perspective for understanding the priorities in the thermal management of high-density packaging and offers a theoretical basis for avoiding indiscriminate optimization efforts on non-critical interfaces.
2. Numerical Model
2.1. Geometric and Material Parameters
The COB light source is an interconnected arrangement of numerous LED chips, comprising metal-based COB arrays, heat sinks, copper coatings, and solder layers [16]. Figure 1 illustrates the LED package structure used in this study. LED chips are bonded via vacuum eutectic using Au-20Sn onto a substrate consisting of a circuit layer, dielectric layer, and metal-aluminum base. Herein, the dielectric layer is specifically the thermally conductive adhesive film. The circuit layer is fabricated with pure copper and features a nickel-palladium-gold (NiPdAu) surface to ensure reliable chip bonding, even under repeated reflow processes. The dielectric layer isolates the metal substrate from the circuit layer, enhancing structural integrity. Other elements, such as soldermask and sealant, are omitted in the FEM simulations due to their negligible thermal impact. A thermal interface material (TIM) connects the aluminum substrate to the heat sink. Table 1 summarizes material properties and dimensional parameters.
Table 1. Dimensions and thermal conductivity of different materials.
| SchemeS. | Thickness (μm) | Size | Materials | Thermal Conductivity (W/mk) |
| Chip | 150 | 1mm×1mm | GaN | 130 |
| Die attach | 10 | 1mm×1mm | Au-20Sn | 57 |
| Circuit | 100 | 20mm×20mm | Cooper | 400 |
| Dielectric | 100 | 20mm×20mm | | 1.1 |
| Substrate | 1500 | 20mm×20mm | Al | 238 |
| TIM | 50 | 20mm×20mm | Thermal grease | 1.5 |
| Heat sink | Base:2mm Fin:8mm | Base:45 mm×100mm Fin:2mm×8mm | Al | 238 |
Figure 1. LED package structure. (a) Schematic model; (b) Structural schematic.
2.2. Assumptions and Governing Equations
The following assumptions have been made:
- (1) The thermal properties of all materials used in this study are assumed to be homogeneous, isotropic and temperature independent.
- (2) In the solid domain (various structural layers of the LED package), heat conduction is described by the following transient heat conduction equation.
- (3) Neglecting thermal radiative dissipation, heat is dissipated around the radiator mainly by convective heat transfer.
The governing equation goes as follows:
The model simulates the temperature distribution inside the LED package. Finite element COMSOL 6.2 software is utilized to create a multi-chip COB LED package. Most of the heat generated by the chips dissipates from the substrate to the area around the heat sink. In the solid domain (various structural layers of the LED package), heat conduction is described by the following transient heat conduction equation [17]:
ρC p (∂T/∂t) = ∇(k · ∇T) + Q
(1)
where k is the thermal conductivity, T is the temperature, ρ is the density, C p is the specific heat capacity, and Q represents the external heat source or power consumption. In addition, the left term is the transient term, which describes the change in temperature with time and contains the density and specific heat capacity of the material, reflecting the storage capacity of thermal energy. The right term is the diffusion term, which describes the heat transfer process and characterizes the thermal conductivity of the material through the thermal conductivity. The temperature gradient drives the heat transfer from high to low temperatures.
The simulation also includes the process of natural convection, and the following is an expression for the governing equation describing the heat transfer between the external element and the air:
ρC p (∂T/∂t + u · ∇T) = ∇·(k∇T) + Q
(2)
where k is the thermal conductivity, T is the temperature, ρ is the density, C p is the specific heat capacity, Q represents the internal heat source, and u is the fluid motion velocity field.
This model employs the “Heat Transfer in Solids and Fluids” interface in COMSOL for conjugate heat transfer calculations, directly coupling Equations (1) and (2). Heat exchange between the outer surface of the heat sink and the surrounding air is implemented by applying Newton’s law of cooling as a boundary condition:
q = h(T j - T a)
(3)
where h is the convection coefficient, T j is the surface temperature, and T a is the ambient temperature.
2.3. Boundary Conditions
(1) The top of each LED chip receives a uniform heat flux of 10 W/m², which is then distributed uniformly over each chip. The LEDs studied in this work have a total wattage of 10 W. Given that the LEDs will operate with 85% of the input power being converted to heat, the heat flux applied to the LED chips is therefore Q = 8.5 W. The uniform distribution of heat flux across all LED chips is a fundamental principle in this study.
(2) The ambient temperature is set to 20 °C. For the radiator, the natural thermal convection coefficient is h = 10 W/m²·K.
(3) The surrounding surfaces of the LED chip, core, core attachment, metallization and substrate are assumed to be adiabatic. In fact, due to their very small area, natural convective heat dissipation and thermal radiation around these components are negligible.
2.4. Discussion on Model Assumptions
The numerical model developed in this study is based on several key assumptions, which, while simplifying the calculations, introduce specific limitations that must be considered when interpreting the results.
First, the model assumes that the heat generation power of the LED chips is fixed at 85% of the input electrical power (corresponding to an electro-optical conversion efficiency of 15%). This is a simplification based on the typical operating point of the chip model under study. In practice, LED efficiency (and thus the proportion of heat generated) varies with driving current and junction temperature. The constant value adopted in this model may lead to deviations in junction temperature estimation under extreme currents or high temperatures. However, since this study primarily conducts a comparative analysis of parameter variations and all compared cases are evaluated under the same input heat generation power, this assumption does not affect the core conclusions regarding the relative influence of adhesive film parameters.
Second, the natural convection heat transfer coefficient on the heat sink surface is set as a constant 10 W/(m²·K) in the model. In reality, this coefficient is a function of the temperature difference between the heat sink surface and the ambient environment. The simplified treatment using a constant value is a reasonable approximation when the heat sink temperature does not vary significantly. However, within the range of junction temperatures simulated in this study (approximately 70 ℃ to 105℃), the temperature of the heat sink baseplate changes accordingly, which may cause slight variations in convective heat transfer intensity. More accurate future studies could treat the heat transfer coefficient as a function of surface temperature.
These simplifications are intended to focus on the influence of the core variables and to manage computational complexity.
3. Results and Discussion
3.1. Numerical Verification
A grid sensitivity study was conducted for the LED package model, in which nine grid divisions were selected for simulation with varying element counts to assess the model’s sensitivity. The stage of leveling off produced a 1.74% change in the LED junction tempera-ture, as shown in Figure 2, where the dashed lines represent the minimum error range.
Figure 2. Mesh sensitivity.
To validate the predictive capability of the numerical simulation, the simulation re-sults under appropriate mesh settings were compared with those obtained from experi-mental samples. The numerical model was constructed based on the actual configuration, also representing a 10 W LED light source mounted on a rectangular heat sink, with con-sistent input power and other parameters. The junction temperature of the LED light source was measured using an LEDT-300B/H junction temperature tester, as shown in Figure 3a. The testing method is based on the electrical test method (forward voltage method) described in the JESD51 standards. First, a small calibration current (Ic) was ap-plied to measure the corresponding junction voltage (Vf) of the LED under test at several different constant temperature points inside a thermal chamber. This established the func-tional relationship between voltage and temperature for the LED, i.e., the voltage-temper-ature coefficient in mV/°C. Subsequently, the LED was operated with its working current (If) to reach normal operating conditions. At regular intervals, the working current If was disconnected. Once thermal equilibrium was achieved under operating conditions, the current was rapidly switched to the calibration current Ic and the junction voltage Vf was measured promptly. In this measurement, the P-N junction serves both as the device un-der test and as the temperature sensor. Temperature changes are reflected in the forward voltage drop across the P-N junction. A computer acquires the voltage data, inserts it into the Tj-Vf curve function defined by the K coefficient, and calculates the junction tempera-ture of the LED P-N junction. Figure 3b shows a schematic diagram of the test connections for the Device Under Test (DUT) inside the thermal chamber. It is then linked to a com-puter via an access port in the oven. The curves depicting the temperature change in the LED light source over time and the simulated transient temperature variation are shown in Figure 4.
Figure 4 presents a comparison of the transient temperature-rise curves between the experiment and the simulation. Overall, the numerical model shows good agreement with the experimental trend and successfully captures the thermal dynamic behavior of the system. However, a consistent deviation is observed. After reaching a steady state, the experimentally measured junction temperature values are consistently 6–7°C(5–7%) higher than the simulation results. This discrepancy can be attributed to several factors: (1) the presence of a phosphor layer and an encapsulating dam structure in the physical sample, which are not accounted for in the simulation model and contribute to additional thermal resistance; (2) the assumption of a constant convective heat transfer coefficient, as noted in Section 2.4, which may not fully capture the actual cooling conditions; and (3) potential minor contact resistances in the experimental setup that are idealized in the sim-ulation. Figure 4 presents a comparison of the transient temperature-rise curves between the experiment and the simulation on a linear time scale, primarily to validate the overall thermal dynamic trend of the model.
It is crucial to acknowledge that the omission of the phosphor layer and encapsulat-ing dam structures in the model introduces a systematic underestimation of the junction temperature by approximately 5–7%. This deliberate simplification was adopted to prior-itize the analysis of the core parameters of interest—namely, the thermal conductivity and thickness of the adhesive film. Notwithstanding this limitation, the model retains signifi-cant value for comparative analysis and the identification of optimal design strategies. This utility is upheld because the relative trends and parametric sensitivity outcomes re-main consistently preserved, thereby offering reliable insights for thermal performance optimization.
Figure 3. (a) Junction temperature tester (Shanghai Leets Lighting Electric Co., Ltd.: Shanghai, China); (b) Connection and Testing.
Figure 3. (a) Junction temperature tester (Shanghai Leets Lighting Electric Co., Ltd.: Shanghai, China); (b) Connection and Testing.
3.2. Thermal Resistance Modeling and Calculation of Thermal Resistance
The heat flow path and thermal resistance network of a single LED chip in the LED package studied in this paper, when the LED array is illuminated, are shown in Figure 5. Where the arrows point to the direction of heat flow, which is similar to a circuit, RLED is the sum of all the thermal resistances from the LED chip heat source to each structure in Figure 6, and its calculation formula is in line with the resistance formula, then the thermal resistance formula can be described through the thermal resistance network as:
P heat = (T j - T a) / [R th,j + R Solder + R Circuit + R Dielectric + R Substrate + R Hs]
(4)
R t = (T j - T a) / P heat
(5)
where T j is the chip junction temperature, T a is the ambient temperature, R th is the chip thermal resistance, R Solder is the solder thermal resistance, R Circuit is the line layer thermal resistance, R Dielectric is the dielectric layer thermal resistance, R Substrate is the substrate thermal resistance, R Hs is the heat sink thermal resistance, P heat is the total input thermal power, and R 1 is the total thermal resistance.
Figure 5. Single-chip thermal resistance network.
Except for the heat source, the thermal resistance of the structure consists of the vertical R 1D in the z-direction and the diffusion thermal resistance R spreading in the x,y-plane, where the thermal diffusion resistance in the x,y-plane depends on the thermal conductivity and thickness of the structure [18-20]. That is:
R = R 1D + R spreading
(6)
R spreading = L / (K A)
(7)
Figure 6. Total thermal resistance network.
The above is the thermal resistance network of a single LED chip, for a pair of chip LED light source, the network diagram of the total thermal resistance of the whole LED package is shown in Figure 6. Then the total thermal resistance formula is as follows:
R total = (Σ i=1n=9 1 / (R LED) i) -1 + R Circuit + R Dielectric + R Substrate + R Hs
(8)
R LED = R Chip + R Solder
(9)
3.3. Simulation Results
Figure 7 displays the steady-state temperature field distribution of the COB LED light source under the default parameters of the adhesive film (thermal conductivity: 1 W/m-K, thickness: 0.1 mm), serving as a benchmark for subsequent parametric studies. To thoroughly investigate the sensitivity of junction temperature to the thermophysical properties of the adhesive film, two sets of controlled-variable experiments were conducted: the first set maintained a constant thickness (0.1mm) while systematically varying the thermal conductivity (k); the second set maintained a constant thermal conductivity (2W/m·K) while systematically varying the thickness (L). The quantitative relationships derived from these investigations are presented in Figure 8. The thermal resistance shown in Figure 8 is that of the thermally conductive adhesive film.
As illustrated in Figure 8a, the junction temperature exhibits a nonlinear decreasing trend as the thermal conductivity of the adhesive film increases. In the low thermal conductivity regime (e.g., increasing from 1 W/m·K to 2 W/m·K), the junction temperature decreases markedly. Calculations based on Equation (7) reveal that the incremental reduction in thermal resistance diminishes with each successive increase in thermal conductivity, resulting in a progressively weaker influence on the junction temperature. When the thermal conductivity of the adhesive film is low, its corresponding thermal resistance acts as the bottleneck in the overall heat dissipation path. Consequently, enhancing k significantly improves the cooling performance. However, once k exceeds a certain threshold, it ceases to be the primary limiting factor, and further optimization of k yields only marginal gains in overall temperature reduction.
Figure 8b demonstrates that within the millimeter-scale thickness range, the junction temperature exhibits an approximately linear relationship with the adhesive film thickness, which aligns well with predictions from theoretical formulas. Given that the adhesive film thickness in practical COB packaging is typically on the micrometer scale, a temperature variation curve at the micrometer level is further plotted in Figure 8c. At this scale, the reduction in thermal resistance achieved by decreasing the thickness remains linear and remarkably significant.
Figure 7. Simulated temperature distribution under standard conditions (Max = 85.5979°C, Min = 56.1790°C).
Figure 8. Temperature variation under different factors: (a) thermal conductivity variation L = 0.1 mm; (b) millimeter-level thickness variation k = 2 W/mK; and (c) micrometer-level thickness varia-tion k = 2 W/mK.
A comparison of the profile shapes in Figure 8a with those in Figure 8b,c indicates that, within the current research scope, the sensitivity of junction temperature variation to thermal conductivity and thickness cannot be directly ascertained solely from the fig-ures. To further quantify the sensitivity of temperature variation to thermal conductivity (K) and thickness (L) within their practical application ranges, the percentage contribution of each parameter was calculated. This study selected five key baseline working points for analysis. The variation ranges of the parameters were defined as follows: thermal conduc-tivity from 1 to 12 W/m·K, and thickness from 0.05 to 0.6 mm. These ranges encompass typical engineering selection limits. For each baseline point, the parameter contribution was computed according to the following formula:
ΔTj(K) =|Tj(Kmax) − Tj(Kmin)| （10）
ΔTj(L) = |Tj(Lmax) − Tj(Lmin)| （11）
contribution = [ΔTj(i)/(ΔTj(K) + ΔTj(L))] × 100% (i = K,L) （12）
The analysis of percentage contributions across five key baseline points clearly re-veals a dynamic shift in the dominance of thermal conductivity (K) and thickness (L) on the junction temperature as the design evolves (The results are shown in Table 2). During the initial design stage, where the thermal resistance of the adhesive film is substantial, thermal conductivity is the dominant parameter governing thermal performance (contrib-uting 54–59.7%). This indicates that selecting a high-thermal-conductivity material is the most effective optimization strategy at this stage. As the K-value increases and the L-value decreases, the system enters an optimized equilibrium zone. Subsequently, the contribu-tion of k peaks and begins to decline, whereas the importance of L steadily increases. This shift signifies that the design focus must transition towards the co-optimization of both K and L.
Table 2. Comprehensive Comparison of Temperature Sensitivity at Different Baseline.
Table 2. Comprehensive Comparison of Temperature Sensitivity at Different Baseline. | Baseline (K,L) | Tj(°C) | ΔTj(K) (°C) | ΔTj(L) (°C) | Contribution (K) | Contribution (L) |
| (2,0.4) | 93.5603 | 24.5817 | 21.0227 | 54% | 46% |
| (4,0.3) | 83.9203 | 21.3821 | 14.4505 | 59.7% | 40.3% |
| (6,0.2) | 78.9354 | 17.3711 | 11.2385 | 60.7% | 39.3% |
| (8,0.1) | 75.6287 | 11.6272 | 9.2535 | 55.7% | 44.3% |
| (10,0.05) | 74.1356 | 7.3092 | 7.8866 | 48.1% | 51.9% |
The aforementioned analysis indicates that reducing the thickness of the adhesive film is an effective approach to enhance thermal efficiency. However, in engineering de-sign, thermal management must be balanced against electrical safety requirements. An excessively thin film may fail to provide sufficient dielectric strength, thereby increasing the risk of electrical breakdown. To investigate this, a series of adhesive film samples with varying thicknesses were prepared by controlling the press-fit process parameters (Table 3). The thermally conductive adhesive film is laminated onto the LED device via this lam-ination process. These process parameters ensured consistent interfacial quality and thick-ness uniformity between the adhesive film and the substrate, providing accurate geomet-ric inputs for subsequent numerical simulations and physical samples for withstand volt-age testing. The samples were subjected to withstand voltage tests in accordance with in-dustry standards (results shown in Table 4). Figure 9 shows the instrumentation used for reliability testing of the packaged substrate. When using the instrument shown in Figure 9, first adjust the instrument to pass the minimum standard voltage. Then place the sub-strate on the platform shown in the figure. At this point, position the test probe on the substrate circuit and apply power for 10 s to pass the test.
Although a thickness of 25 µm can provide a lower junction temperature, its risk of insulation failure renders it unsuitable for practical applications. Therefore, when select-ing the adhesive film thickness in design, it is imperative to first satisfy the insulation lower limit (approximately ≥ 35 µm). Under this constraint, thermal performance should be optimized: for instance, opting for a thickness of 50 µm (with a thermal conductivity of 2 W/m·K) can yield a junction temperature approximately 4°C lower than that of a 100 µm thickness while ensuring adequate insulation. If thermal budgets are extremely strin-gent, considering adhesive materials with higher dielectric strength may permit the use of thinner layers (e.g., 35–40 µm), though this necessitates re-validation through with-stand voltage testing.
Table 3. Press-fit program. | Step | 01 | 02 | 03 | 04 | 05 | 06 | 07 | 08 | 09 |
| Press kg/cm² | 20 | 20 | 30 | 30 | 30 | 40 | 40 | 40 | 40 |
| Temp /°C | 130 | 145 | 165 | 175 | 195 | 200 | 200 | 100 | 60 |
| Time /h | 0.02 | 0.1 | 0.15 | 0.1 | 0.3 | 0.2 | 1.2 | 0.3 | 0.2 |
Figure 9. Schematic diagram of the withstanding voltage tester (Shenzhen Pinhong Technology Co., Ltd., Shenzhen, China) used to evaluate the insulation strength of adhesive film samples.
Table 4. Voltage withstand test results. | Sample | 25 μm | 35 μm | 50 μm | 75 μm | 90 μm |
| Max Voltage /KV(10 s) | 1.9 | 2.5 | 2.8 | 3 | 3.5 |
| Pass Voltage/KV(10 s) | 2 | 2 | 2 | 2 | 2 |
| Result | Fail | Pass | Pass | Pass | Pass |
3.4. Sensitivity of Chip Pitch and Number of Chips to Changes in Thermal Conductivity and Thickness of Adhesive Film
The distribution of LED chips on the substrate exerts a distinct influence on the over-all junction temperature change. To ascertain the extent to which thermal conductivity and adhesive film thickness affect junction temperature, the temperature profile is ob-tained by varying chip pitches from 0.8 mm to 3.3 mm based on the chip 3 × 3 arrange-ment. A schematic diagram of the chip spacing is shown in Figure 10. Figure 11 illustrates the temperature profile based on the chip 3 × 3 arrangement at varying chip pitches. As illustrated in the figure, in the case of a reduced chip pitch, the thermal diffusion in the horizontal plane of the substrate exhibits greater interference, thereby making the thermal conductivity of the film and the junction temperature of the substrate more discernible. In the 0.8 mm pitch configuration, the thermal conductivity undergoes an increase from 1 W/mK to 6 W/mK to 12.7%, while the thickness undergoes a change from 0.05 mm to 0.6 mm to 30.3%. The augmentation of the chip pitch has been demonstrated to enhance the heat diffusion capability, thereby reducing the adhesive film’s impact on temperature. This progression culminates in a gradual and uniform temperature change.
Figure 10. Chip pitch diagram (unit: mm).
Figure 11. Temperature profiles at different chip pitches: (a) thermal conductivity variation L = 0.1 mm; (b) millimeter-level thickness variation k = 2 W/mK; and (c) micrometer-level thickness varia-tion k = 2 W/mK.
In addition to the different effects of chip pitch on the overall junction temperature variation, the different sizes of chips also have an effect on the overall junction temperature variation. Ying [21] et al. investigated the overall junction temperature with different sizes of chips, and the results showed that the maximum junction temperature of multi-chip COB LED increases with the decrease in the number of chips. Similarly, in order to study the temperature sensitivity in this case under the variation in thermal con-ductivity and thickness of the adhesive film, the total chip area and input power are fixed, and the number of chips is divided into 4, 9, 16, and 25. The chip pitch of each group is fixed to 1.3 mm. Numerical simulations are carried out under this condition, and the re-sults of the simulations are shown in Figure 12. Figure 13 demonstrates the variation in temperature with thermal conductivity parameters under different chip counts.
Figure 12. Temperature evolution on the LED package for different numbers; pitch: 1.3 mm.
Figure 13. Temperature profile with different numbers of chips; (a) thermal conductivity variation L = 0.1 mm; (b) millimeter-level thickness variation k = 2 W/mK; and (c) micrometer-level thickness variation k = 2 W/mK.
A comparison with the temperature curves in Figure 11 shows that they all share the same trend. That is to say, when the temperature is high, the sensitivity of the temperature to the thermal conductivity and thickness of the adhesive film is the highest, and the role of the adhesive film is also reflected under these conditions. But when the thermal con-ductivity gradually increases, while the temperature decreases, the temperature change caused by the adhesive film becomes very small. Even if the thermal conductivity of the adhesive film continues to be increased, its impact on the overall temperature of the COB light source becomes very small, manifested as a very small change in the temperature drop rate. The same principle applies to the change in thickness.
In summary, when altering the thermal conductivity or thickness of the adhesive film, the initial modification can disrupt the original thermal equilibrium, leading to a decrease in temperature. However, as one factor is continuously optimized, the entire sys-tem tends toward a new equilibrium. At this point, other factors become the key con-straints limiting heat dissipation effectiveness, resulting in a convergent influence of both parameters on temperature during the later stages of their respective variations.
Similarly, as can also be observed from Figures 11 and 13, in cases of denser chip distribution, the initial change in the thermal resistance of the adhesive film has the most significant impact on temperature variation. A reduction in chip spacing or in the number of chips—while maintaining high power per chip—leads to concentrated heat distribution and restricted lateral diffusion. This makes the thermal resistance of the adhesive film the dominant factor in the heat dissipation chain. By reducing the thermal resistance of the adhesive film, such as by using adhesives with higher thermal conductivity or reducing the thickness, the heat accumulation under dense layouts can be prioritized and effec-tively mitigated, thereby significantly enhancing the heat dissipation efficiency.
3.5. Mechanism Analysis: Thermal Resistance Network and Bottleneck Shift
The trends observed in Figure 8 can be quantitatively interpreted using the thermal resistance network model established in Section 3.2. According to Equations (6) and (7),the thermal resistance of the adhesive film Rotelectric is expressed as RDielectric = where L is the thickness and k is the thermal conductivity. This inverse relationship with k and direct proportionality to L fundamentally accounts for the nonlinear and linear trends observed in Figure 8a and Figure 8b, respectively. Furthermore, Rpialectric domi-nates the Rearat when k is relatively low (e. g.,<2W/m·K) or Lis comparatively large(e. g.,>0.3mm).
To more intuitively demonstrate the dominant role of Rositavi, based on the data inTable 1 and Equation (9), the thermal resistances of all components except Revep were calculated. Given that each component within the package constitutes a homogeneous layer, the thermal resistance of each part can be determined according to Equation (7). The heat sink, serving as a means of optimizing heat dissipation, was excluded from the equiv-alent thermal resistance calculation. The results indicate that Rosumnic-0.227 K/W plays a dominant role in the overall thermal resistance network. Additionally, Table 5 was con-structed to illustrate the variation in Rrotal as a function of the optimization of Rowance.The optimization was performed by enhancing the thermal conductivity of the thermal adhesive film.
Therefore, reducing R Dielectric directly and significantly decreases the total thermal resistance, resulting in a lower junction temperature. This effect is evidenced by the steep initial slope of the curves. However, the observed phenomenon of diminishing returns originates from a shift in the thermal bottleneck. As expressed by Equation (9), the total thermal resistance represents a series summation of multiple individual resistances. Once R Dielectric is substantially reduced, it ceases to be the dominant resistance in the series network. Consequently, the primary thermal bottleneck shifts to other components within the system, such as the substrate resistance R subscribe , the thermal interface material resistance R TIM , the heatsink resistance R Hs , or even the convective resistance R conv . Further optimization of the adhesive film yields minimal reduction in the total thermal resistance,as the remaining thermal resistances become the dominant factor governing the heat flow.This rationale explains the plateau region in Figure 8a and the convergent influence of both parameters on junction temperature reduction during the later stages of optimiza-tion.
To better elucidate this thermal bottleneck transition, a three-dimensional surface plot(Figure 14) was generated to visualize the junction temperature as a function of both thermal conductivity (k) and thickness (L). This visualization integrates the influence of both parameters, enabling a combined assessment of their impact on junction tempera-ture, identification of critical thermal bottleneck regions, and exploration of their interac-tive effects.
Figure 14. Three-dimensional surface plot of junction temperature versus K and L.
Figure 14 clearly demonstrates that the rate of reduction in junction temperature di-minishes significantly after a certain degree of optimization. When the thermal conduc-tivity of the adhesive film is below3W/m·K and its thickness exceeds 200μm, the junction temperature is highly sensitive to the film's parameters, indicating that the adhesive film constitutes the absolute dominant thermal bottleneck within the system. Operating within this region, increasing the thermal conductivity (k) or reducing the thickness (L) yields the maximum improvement in thermal performance. Conversely, when the thermal con-ductivity is increased beyond 5 W/m-K and the thickness is reduced below 100μm,(T=76.9451°C), the change in junction temperature plateaus. This trend indicates that the the r-mal resistance of the adhesive film has been sufficiently optimized, and the primary ther-mal bottleneck has consequently shifted to other components within the system.
This mechanism of bottleneck shift is particularly pronounced in dense chip layouts,as shown in Figures 11 and 13. In high-power-density configurations(with small pitch or a large number of chips), heat flux becomes concentrated, and the lateral spreading re-sistance within the substrate increases significantly. This markedly raises the local thermal resistance faced by each chip, making the vertical heat transfer path through the underly-ing adhesive film even more critical. Thus, in dense arrays, the adhesive film becomes the primary bottleneck at an earlier stage. Optimizing its parameters in such scenarios yields the most substantial thermal improvement, as it directly alleviates the most severe limita-tion in the heat transfer path. Once the film resistance is minimized, the bottleneck shifts to the lateral heat spreading capability of the substrate or the overall capacity of the heat sink, which are less sensitive to the properties of the adhesive film. A schematic illustra-tion of this thermal bottleneck shift is provided in Figure 15.
Figure 15. Schematic of thermal bottleneck shift. (a) Film as bottleneck. (b) Bottleneck shifted.
Based on the numerical simulations and thermal resistance network analysis con-ducted in this study, a generalized workflow for identifying and optimizing thermal bot-tlenecks in LED packaging is proposed, aiming to provide methodological guidance for thermal management design across various packaging scenarios: (1) establish and vali-date a parameterized thermal model; (2) construct and quantify the thermal resistance network;(3) identify the current dominant thermal bottleneck by comparing thermal re-sistance values and performing sensitivity analysis;(4) implement targeted parameter op-timization for the bottleneck stage; and (5) evaluate the optimization effectiveness and re-identify new potential bottlenecks for iterative refinement.
This study enhances the reliability of COB LED packages by optimizing the parame-ters of the thermally conductive adhesive film to mitigate its effect as a thermal imperfec-tion (high thermal resistance). This imperfection minimization paradigm is fundamental for ensuring the long-term stable operation of electronic devices. Notably, a complemen-tary paradigm exists for understanding and managing imperfections or non-idealities. As revealed by Bucolo et al. [22] in the field of circuit design, inherent structural imperfec-tions from the manufacturing process (e. g., parasitic elements) can, under specific condi-tions, be intentionally leveraged to become the key to exciting complex and beneficial dy-namic behaviors, such as chaos. This suggests that imperfections possess a duality: they can be a performance bottleneck, but also a potential resource for new functionalities when sufficiently understood.
Extending this perspective to the field of electronic packaging thermal management,a more comprehensive imperfection co-design approach is worth exploring. The first as-pect is mitigative design, which focuses on optimizing dominant, detrimental imperfec-tions, such as the high interfacial thermal resistance addressed in this work. The second is cognitive and adaptive design, which involves fully characterizing the parameters of sto-chastic, hard-to-eliminate imperfections inherent to the process and incorporating them as known inputs into robustness design and lifetime prediction models. This study fo-cuses on the first paradigm, clarifying the optimization path and limits for a key thermal imperfection. The thermal bottleneck shifted phenomenon observed during this research is a dynamic system response during the sequential optimization of imperfections. This provides methodological insights for understanding more complex multi-imperfection in-teractions and system-level reliability design.
4. Conclusions
This study conducted a series of research work from model validation to mechanistic analysis, focusing on the impact of thermally conductive adhesive films on the thermal reliability of multi-chip COB LED packages. The main conclusions are as follows:
We successfully constructed and experimentally validated a three-dimensional finite element model. Although this model did not account for secondary structures such as the phosphor layer—resulting in a systematic underestimation of the junction temperature by approximately 5–7%—its predicted trends showed high consistency with experimental results, providing a reliable foundation for subsequent parametric analysis and mechanistic research.
Systematic simulation results indicated that optimizing both the thermal conductiv-ity and thickness of the adhesive film can effectively reduce the junction temperature. The study found that when k exceeds approximately 5 W/m·K or L is reduced below approximately 0.1 mm, the thermal improvement gained from further optimization diminishes significantly. Furthermore, through additional numerical simulations in-volving changes in chip spacing and fixed chip area with varying numbers of chips, the results demonstrated that the sensitivity of junction temperature to the thermal conductivity and thickness of the adhesive film is higher in configurations with more concentrated temperature distribution. Based on the thermal resistance network model, this study revealed the core mechanism of thermal bottleneck shift: once the thermal resistance of the adhesive film is sufficiently optimized, the dominant bottleneck in the heat dissipation path shifts to subsequent components such as the substrate or heat sink. This mechanism rationally explains the phenomenon of diminish-ing returns observed during parametric optimization and provides an important the-oretical basis for the thermal design of high-density packaging.
Future research could focus on developing new high-performance adhesive film ma-terials and validating their long-term reliability under more complex operating con-ditions.
Through its layered and progressive analysis, this paper not only provides practical guidelines for optimizing adhesive film parameters in COB LED packaging but, more im-portantly, reveals the fundamental principle of dynamic thermal bottleneck shift, which offers universally applicable guidance for the field of electronic packaging thermal design.
Author Contributions: T.W.: Conceptualization, Methodology, Software, Investigation, Formal Anal-ysis, Writing—Original Draft; J.S.: Data Curation; P.W.: Visualization, Investigation; Y.L.: Resources, Supervision; J.Z.: Conceptualization, Funding Acquisition, Resources, Supervision, Writing—Review and Editing. All authors have read and agreed to the published version of the manuscript.
Funding: National Key R&D Program of China (2021YFB3501700), Shanghai Science and Technol-ogy Committee (STCSM) Science and Technology Innovation Program (23N21900100,22N21900400), National Natural Science Foundation of China (12104311), Key R&D Program of Zhejiang Province (2024C01193), Shanghai Chenguang Program (22CGA74), Key R&D Program of Jiangsu Province (BE2023048), and Yunnan Province Innovation Guidance and Technology oriented Enterprise Cul-tivation Plan (202404BI090001).
Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.
Data Availability Statement: The original contributions presented in this study are included in the article. Further inquiries can be directed to the corresponding author.
Acknowledgments: Dasheng Dong and Shufu Jiang.
Conflicts of Interest: Author Yitao Liao was employed by the company Xuzhou Liyu Advanced Technology. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.
References
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16. Elnouino, H.; Bendaou, O. Numerical Study on the Effect of Thermal Pad on Thermal Management of Multi-Chip LED COB. In 2024 Mediterranean Smart Cities Conference (MSCC); IEEE: Piscataway, NJ, USA, 2024; pp. 1–6. https://doi.org/10.1109/mscc62288.2024.1069700.
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18. Yang, K.; Chung, C.; Tu, C.; Wong, C.; Yang, T.; Lee, M. Thermal spreading resistance characteristics of a high power light emitxting diode module. Appl. Therm. Eng. 2014, 70, 361–368. https://doi.org/10.1016/j.applthermaleng.2014.05.028.
19. Wu, H.; Lin, K.; Lin, S. A study on the heat dissipation of high power multi-chip COB LEDs. Microelectron. J. 2012, 43, 280–287. https://doi.org/10.1016/j.mejo.2012.01.007.
20. Chen, Y.; Chien, K.; Tseng, Y.; Chan, Y. Determination of optimized rectangular spreader thickness for lower thermal spreading resistance. J. Electron Packag. 2009, 131, 011004. https://doi.org/10.1115/1.3068299.
21. Ying, N.S.; Shen, N.W. Thermal analysis of High-Power Multichip COB diodes with different chip sizes. IEEE Trans. Electron Devices 2015, 62, 896–901.
22. Bucolo, M.; Buscarino, A.; Famoso, C.; Fortuna, L.; Gagliano, S. Imperfections in integrated devices allow the emergence of unexpected strange in electronic circuits. IEEE Access 2021, 9, 29573–29583.
1. Steigerwald, D.; Bhat, J.; Collins, D.; Fletcher, R.; Holcomb, M.; Ludowise, M.; Martin, P.; Rudaz, S. Illumination with solid state lighting technology. IEEE J. Sel. Top. Quantum Electron. 2002, 8, 310–320. https://doi.org/10.1109/2944.999186.
2. Narendran, N.; Gu, Y.; Freyssinier, J.; Yu, H.; Deng, L. Solid-state lighting: Failure analysis of white LEDs. J. Cryst. Growth 2004, 268, 449–456. https://doi.org/10.1016/j.jcrysgro.2004.04.071.
3. Xi, Y.; Schubert, E.F. Junction–temperature measurement in GaN ultraviolet light-emitting diodes using diode forward voltage method. Appl. Phys. Lett. 2004, 85, 2163–2165. https://doi.org/10.1063/1.1795351.
4. Zhao, L.X.; Thrush, E.J.; Humphreys, C.J.; Phillips, W.A. Degradation of GaN-based quantum well light-emitting diodes. J. Appl. Phys. 2008, 103, 024501. https://doi.org/10.1063/1.2829781.
5. Yang, P.; Liao, N. Physical mechanism of interfacial thermal resistance in electronic packaging based on a mixed MD/FE model. IEEE Trans. Adv. Packag. 2008, 31, 496–501. https://doi.org/10.1109/tadvp.2008.927830.
6. Bang, Y.; Moon, C. Enhancement of upward thermal dissipation in a 16-Chip LED package using ceramic barrier ribs. Electron. Mater. Lett. 2013, 9, 1–5. https://doi.org/10.1007/s13391-013-3177-0.
7. Xia, Z.; Liang, S.; Li, B.; Wang, F.; Zhang, D. Influence on temperature distribution of COB deep UV LED due to different packaging density and substrate type. Optik 2021, 231, 166392. https://doi.org/10.1016/j.ijleo.2021.166392.
8. Wang, Z.; Li, Y.; Zou, J.; Yang, B.; Shi, M. Effect of different soldering temperatures on the properties of COB light source. Solder. Surf. Mt. Technol. 2021, 34, 88–95. https://doi.org/10.1108/ssmt-03-2021-0010.
9. Yu, X.; Xiang, L.; Zhou, S.; Pei, N.; Luo, X. Realization of microlens array on flat encapsulant layer for enhancing light efficiency of COB-LEDs. IEEE Photonics Technol. Lett. 2020, 32, 1315–1318. https://doi.org/10.1109/lpt.2020.3022794.
10. Lee, C.K.; Ahn, J.K.; Lee, C.R.; Kim, D.; Baek, B.J. Thermal analysis of LED lamp with LTCC-COB package. Microelectron. Int. 2013, 30, 3–9. https://doi.org/10.1108/13565361311298169.
11. Kim, Y.; Kim, Y.; Ko, S. Thermal characteristics and fabrication of silicon sub-mount based LED package. Microelectron. Reliab. 2015, 56, 53–60. https://doi.org/10.1016/j.microrel.2015.10.010.
12. Jiang, Y.; Bark, H.; Huang, P.; Hu, T.; Li, Y.; Lee, P.S. Printable Boron Nitride–Liquid Metal Hybrid thermal interface materials for advanced electronics. ACS Appl. Mater. Interfaces 2025, 17, 59810–59822. https://doi.org/10.1021/acsami.5c15539.
13. Kim, Y.G.; Jung, I.; Mun, Y.; Shin, J.H.; Lee, S.G.; Koirala, G.R.; Kang, T.; Ok, J.; Choi, H.; Kim, J.; et al. Bi-Directional assembly of boron nitride Μ-Platelets by Micro-Molding for advanced thermal interface materials. Adv. Funct. Mater. 2025, 35, 2421607. https://doi.org/10.1002/adfm.202421607.
14. Chen, M.; Zhou, Z.; Wang, X.; Zhao, Y.; Zhou, Y. Performance Study of Diamond Powder-Filled Sodium Silicate-Based Thermal Conductive Adhesives. Materials 2023, 16, 3937. https://doi.org/10.3390/ma16113937.
15. Wang, X.; Zhang, C.; Zhang, T.; Tang, C.; Chi, Q. Enhanced thermal conductivity of epoxy resin by incorporating three-dimensional boron nitride thermally conductive network. J. Chem. Phys. 2024, 160, 154903. https://doi.org/10.1063/5.0205196.
16. Elnouino, H.; Bendaou, O. Numerical Study on the Effect of Thermal Pad on Thermal Management of Multi-Chip LED COB. In 2024 Mediterranean Smart Cities Conference (MSCC); IEEE: Piscataway, NJ, USA, 2024; pp. 1–6. https://doi.org/10.1109/mscc62288.2024.1069700.
17. Bergman, T.L.; Lavine, A.S.; Incropera, F.P.; DeWitt, D.P. Fundamentals of Heat and Mass Transfer, 8th ed.; Wiley: Hoboken, NJ, USA, 2018. Available online: https://www.wiley.com/en-cn/Fundamentals+of+Heat+and+Mass+Transfer%2C+8th+Edition-p9781119353881 (accessed on 26 April 2026).
18. Yang, K.; Chung, C.; Tu, C.; Wong, C.; Yang, T.; Lee, M. Thermal spreading resistance characteristics of a high power light emitxting diode module. Appl. Therm. Eng. 2014, 70, 361–368. https://doi.org/10.1016/j.applthermaleng.2014.05.028.
19. Wu, H.; Lin, K.; Lin, S. A study on the heat dissipation of high power multi-chip COB LEDs. Microelectron. J. 2012, 43, 280–287. https://doi.org/10.1016/j.mejo.2012.01.007.
20. Chen, Y.; Chien, K.; Tseng, Y.; Chan, Y. Determination of optimized rectangular spreader thickness for lower thermal spreading resistance. J. Electron Packag. 2009, 131, 011004. https://doi.org/10.1115/1.3068299.
21. Ying, N.S.; Shen, N.W. Thermal analysis of High-Power Multichip COB diodes with different chip sizes. IEEE Trans. Electron Devices 2015, 62, 896–901.
22. Bucolo, M.; Buscarino, A.; Famoso, C.; Fortuna, L.; Gagliano, S. Imperfections in integrated devices allow the emergence of unexpected strange in electronic circuits. IEEE Access 2021, 9, 29573–29583.
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